HD64F36024FX Datasheet, PDF (102/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Power-Down Modes
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
DTON
SSBY
Transition Mode after SLEEP Transition Mode due to
SMSEL Instruction Execution
Interrupt
0
0
0
Sleep mode
Active mode
0
1
Subsleep mode
Active mode
1
X
Standby mode
Active mode
1
X
0*
Active mode (direct transition) —
Legend:
*
X: Don’t care.
When a state transition is performed while SMSEL is 1, timer V, SCI3, SCI3_2, SCI3_3
(only for the H8/36024) and the A/D converter are reset, and all registers are set to their
initial values. To use these functions after entering active mode, reset the registers.
Table 6.3 Internal State in Each Operating Mode
Function
System clock oscillator
CPU
Instructions
operations _Registers
RAM
IO ports
Active Mode
Functioning
Functioning
Functioning
Functioning
Functioning
Sleep Mode
Functioning
Halted
Retained
Retained
Retained
Subsleep Mode
Halted
Halted
Retained
Retained
Retained
External
interrupts
IRQ3, IRQ0
WKP5 to
WKP0
Peripheral Timer V
functions _{Timer W}
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Reset
Retained
Watchdog
timer
Functioning Functioning Retained
SCI3
Functioning
A/D converter Functioning
Functioning
Functioning
Reset
Reset
Standby Mode
Halted
Halted
Retained
Retained
Register contents are
retained, but output is the
high-impedance state.
Functioning
Functioning
Reset
Retained (if internal clock
φ is selected as a count
clock, the counter is
incremented by a
subclock)
Retained (functioning if the
internal oscillator is
selected as a count clock)
Reset
Reset
Rev. 4.00 Sep. 23, 2005 Page 74 of 354
REJ09B0025-0400