HD64F36024FX Datasheet, PDF (93/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system
clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a
duty correction circuit, and system clock dividers.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC₁
OSC₂
System
clock
oscillator
φ_OSC
(f_OSC)
Duty
correction
circuit
φ_OSC
(f_OSC)
System clock pulse generator
System
clock
divider
φ_OSC
φ_OSC/8
φ_OSC/16
φ_OSC/32
φ_OSC/64
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are system clocks (φ).
The system clock is divided into φ/8192 to φ/2 by prescaler S and they are supplied to respective
peripheral modules.
5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generator.
OSC ₂
OSC ₁
LPM
LPM: Low-power mode (standby mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator
CPG0200A_000020020200
Rev. 4.00 Sep. 23, 2005 Page 65 of 354
REJ09B0025-0400