HD64F36024FX Datasheet, PDF (22/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 13.9 Data Format in Clocked Synchronous Communication .......................................... 200
Figure 13.10 Example of SCI3 Transmission in Clocked Synchronous Mode .......................... 202
Figure 13.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 202
Figure 13.12 Example of SCI3 Reception in Clocked Synchronous Mode................................ 203
Figure 13.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 204
Figure 13.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)............................................................................... 206
Figure 13.15 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 208
Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 209
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 211
Figure 13.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 212
Figure 13.18 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 213
Figure 13.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 216
Section 14 A/D Converter
Figure 14.1 Block Diagram of A/D Converter ........................................................................... 218
Figure 14.2 A/D Conversion Timing.......................................................................................... 224
Figure 14.3 External Trigger Input Timing ................................................................................ 225
Figure 14.4 A/D Conversion Accuracy Definitions (1).............................................................. 227
Figure 14.5 A/D Conversion Accuracy Definitions (2).............................................................. 227
Figure 14.6 Analog Input Circuit Example ................................................................................ 228
Section 15 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 15.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 230
Figure 15.2 Operational Timing of Power-On Reset Circuit...................................................... 233
Figure 15.3 Operational Timing of LVDR Circuit ..................................................................... 234
Figure 15.4 Operational Timing of LVDI Circuit ...................................................................... 235
Figure 15.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 236
Section 16 Power Supply Circuit
Figure 16.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 237
Figure 16.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 238
Section 18 Electrical Characteristics
Figure 18.1 System Clock Input Timing .................................................................................... 281
Figure 18.2 RES Low Width Timing.......................................................................................... 282
Figure 18.3 Input Timing............................................................................................................ 282
Figure 18.4 SCK3 Input Clock Timing ...................................................................................... 282
Figure 18.5 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 283
Figure 18.6 Output Load Circuit ................................................................................................ 283
Rev. 4.00 Sep. 23, 2005 Page xx of xxvi