HD64F36024FX Datasheet, PDF (19/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 3
Figure 1.2 Pin Arrangement (FP-64E)............................................................................................ 4
Figure 1.3 Pin Arrangement (FP-48F, FP-48B, TNP-48)............................................................... 5
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 10
Figure 2.1 Memory Map (2) ......................................................................................................... 11
Figure 2.2 CPU Registers ............................................................................................................. 12
Figure 2.3 Usage of General Registers ......................................................................................... 13
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 14
Figure 2.5 General Register Data Formats (1).............................................................................. 16
Figure 2.5 General Register Data Formats (2).............................................................................. 17
Figure 2.6 Memory Data Formats................................................................................................. 18
Figure 2.7 Instruction Formats...................................................................................................... 29
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 33
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 35
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 36
Figure 2.11 CPU Operation States................................................................................................ 37
Figure 2.12 State Transitions ........................................................................................................ 38
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 39
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 54
Figure 3.2 Stack Status after Exception Handling ........................................................................ 56
Figure 3.3 Interrupt Sequence....................................................................................................... 57
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 58
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 59
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 63
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 63
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 65
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 65
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 66
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 66
Rev. 4.00 Sep. 23, 2005 Page xvii of xxvi