HD64F36024FX Datasheet, PDF (109/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 ROM
7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit
7 to 5
Initial
Bit Name Value
—
All 0
4
EB4
0
3
EB3
0
2
EB2
0
1
EB1
0
0
EB0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0.
When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
7.2.4 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
Initial
Bit
Bit Name Value
7
FLSHE 0
6 to 0 —
All 0
R/W
R/W
—
Description
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
Reserved
These bits are always read as 0.
Rev. 4.00 Sep. 23, 2005 Page 81 of 354
REJ09B0025-0400