HD64F36024FX Datasheet, PDF (133/386 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 9 I/O Ports
9.3.3 Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Initial
Bit
Bit Name Value R/W Description
7
P57
0
R/W Stores output data for port 5 pins.
6
P56
0
5
P55
0
4
P54
0
3
P53
0
R/W If PDR5 is read while PCR5 bits are set to 1, the value
R/W ^{stored in PDR5 are read. If PDR5 is read while PCR5 bits}
are cleared to 0, the pin states are read regardless of the
R/W _{value stored in PDR5.}
R/W
2
P52
0
R/W
1
P51
0
R/W
0
P50
0
R/W
9.3.4 Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Initial
Bit
Bit Name Value R/W Description
7, 6 
All 0

Reserved
These bits are always read as 0.
5
PUCR55 0
4
PUCR54 0
3
PUCR53 0
2
PUCR52 0
R/W Only bits for which PCR5 is cleared are valid. The pull-up
R/W ^{MOS of the corresponding pins enter the on-state when}
these bits are set to 1, while they enter the off-state when
R/W _{these bits are cleared to 0.}
R/W
1
PUCR51 0
R/W
0
PUCR50 0
R/W
Rev. 4.00 Sep. 23, 2005 Page 105 of 354
REJ09B0025-0400