4552 Datasheet, PDF (95/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction
code
D9
D0
Number of
1001110000
270
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T17–T14)
(A) ← (T13–T10)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T17–T14) of
timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of
timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction
code
D9
D0
Number of
1001110001
271
2
16
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (T27–T24)
(A) ← (T23–T20)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T27–T24) of
timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of
timer 2 to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction
code
D9
D0
Number of
0 0 0 0 1 0 1 0 1 0 ₂ 0 2 A ₁₆
words
1
Number of
cycles
1
Flag CY
–
Skip condition
–
Operation:
(B) ← (E7–E4)
(A) ← (E3–E0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction
code
D9
D0
Number of Number of Flag CY
0
0
1
0
p5 p4 p3 p2 p1 p0 ₂
0
8
+p
p ₁₆
words
cycles
1
3
–
Skip condition
–
Operation:
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note)
(PCL) ← (DR2–DR0, A3–A0)
at (UPTF) = 0
at (UPTF) = 1
(B) ← (ROM(PC))7–4 (DR2) ← (0)
(A) ← (ROM(PC))3–0 (DR1, DR0) ← (ROM(PC))9, 8
(B) ← (ROM(PC))7–4
(A) ← (ROM(PC))3–0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Grouping: Arithmetic operation
Description:
UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits
9 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p.
UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to
register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2
A1 A0)2 specified by registers A and D in page p.
Note: p is 0 to 31 for M34552M4/M4H, and p is 0 to 63 for M34552M8/M8H/G8/G8H.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
Rev.3.02 Dec 22, 2006 page 95 of 142
REJ03B0023-0302