4552 Datasheet, PDF (27/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(3) Notes on External 0 interrupts
➀ Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
➂ Note on bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
• Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 18➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 18➂).
• Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 20➂).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; (1✕✕✕2)
; Control of INT pin input is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (✕✕✕02)
; The SNZ0 instruction is valid ........... ➀
; Interrupt valid waveform is changed
........................................................... ➁
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... ➂
✕ : these bits are not used here.
Fig. 18 External 0 interrupt program example-1
✕ : these bits are not used here.
Fig. 20 External 0 interrupt program example-3
➁ Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
• When the key-on wakeup function of INT pin is not used (register
K20 = “0”), clear bits 2 and 3 of register I1 before system enters
to the power down mode. (refer to Figure 19➀).
LA 0
TI1A
DI
EPOF
POF2
; (00✕✕2)
; Input of INT disabled ........................ ➀
; power down mode
✕ : these bits are not used here.
Fig. 19 External 0 interrupt program example-2
Rev.3.02 Dec 22, 2006 page 27 of 142
REJ03B0023-0302