4552 Datasheet, PDF (6/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
DEFINITION OF CLOCK AND CYCLE
q Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external RC oscillation
• Clock (f(XIN)) by the external input
• Clock (f(RING)) of the on-chip oscillator which is the internal
oscillator
• Clock (f(XCIN)) by the external quartz-crystal resonator
Table Selection of system clock
Register MR
System clock
MR3 MR2 MR1 MR0
1
1
0
0 f(STCK) = f(RING)/8
1
0
0
0 f(STCK) = f(RING)/4
0
1
0
0 f(STCK) = f(RING)/2
0
0
0
0 f(STCK) = f(RING)
1
1
0
1 f(STCK) = f(XIN)/8
1
0
0
1 f(STCK) = f(XIN)/4
0
1
0
1 f(STCK) = f(XIN)/2
0
0
0
1 f(STCK) = f(XIN)
1
1
1
0 f(STCK) = f(XCIN)/8
1
0
1
0 f(STCK) = f(XCIN)/4
0
1
1
0 f(STCK) = f(XCIN)/2
0
0
1
0 f(STCK) = f(XCIN)
q System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
q Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle gen-
erates the one machine cycle.
q Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Operation mode
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
Note: The f(RING)/8 is selected after system is released from reset.
PORT FUNCTION
Port
Pin
Port D D0–D4, D5/INT
Input
Output
I/O
(6)
Output structure
N-channel open-drain/
CMOS
XCIN/D6, XCOUT/D7
Port P0 P00/SEG21–P03/SEG24
Output
(2)
I/O
(4)
N-channel open-drain
N-channel open-drain/
CMOS
Port P1 P10/SEG25–P13/SEG28 I/O N-channel open-drain/
(4) CMOS
Port P2 P20/SEG17–P23/SEG20
Port C C/CNTR
I/O
(4)
Output
(1)
N-channel open-drain/
CMOS
CMOS
I/O
Control
Control
unit instructions registers
Remark
1 SD, RD FR1, FR2 Output structure selection
SZD
I1, K2
function (programmable)
CLD
RG
4 OP0A
IAP0
4 OP1A
IAP1
4 OP2A
IAP2
1 RCP
SCP
FR0, PU0
K0
C1
FR0, PU1
K0, K1
C2
FR2
L3
W1
Built-in pull-up functions, key-on
wakeup functions and output
structure selection function
(programmable)
Built-in pull-up functions, key-on
wakeup functions and output
structure selection function
(programmable)
Output structure selection func
tion (programmable)
Rev.3.02 Dec 22, 2006 page 6 of 142
REJ03B0023-0302