4552 Datasheet, PDF (51/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
VOLTAGE DROP DETECTION CIRCUIT
(only for H version)
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply voltage
drops below a set value.
(1) SVDE instruction
When the SVDE instruction is executed, the voltage drop deteciton
circuit is valid even after system enters into the power down mode.
The SVDE instruction can be executed only once.
In order to release the execution of the SVDE instruction, the sys-
tem reset is required.
S
QR
QS
R
EPOF instruction +POF instruction
EPOF instruction +POF2 instruction
Internal reset signal
T3F flag
Key-on wakeup signal
SVDE instruction
Internal reset signal
–
VRST +
Voltage drop detection circuit
Fig. 41 Voltage drop detection reset circuit
VDD
VRST+(reset release voltage)
VRST ^-(reset occurrence voltage)
Voltage drop detection circuit
Reset signal
RESET pin
Voltage drop detection circuit
Reset signal
Microcomputer starts operation after
on-chip oscillator (internal oscillator)
clock is counted 1376 times.
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
Fig. 42 Voltage drop detection circuit operation waveform
(2) Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this prod-
uct is set up lower than the minimum value of the supply voltage
of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and re-
goes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added
to the power supply pin, the following case may cause program
failure (Figure 43);
supply voltage does not fall below to VRST-, and
its voltage re-goes up with no reset.
In such a case, please design a system which supply voltage is
once reduced below to VRST- and re-goes up after that.
VDD
Recommended
operatng condition
min.value
VV^{RRSSTT+–}
No reset
Program failure may occur.
VDD
Recommended
operatng condition
min.value
VV^{RRSSTT+–}
Reset
→ Normal operation
Fig. 43 VDD and VRST^–
Rev.3.02 Dec 22, 2006 page 51 of 142
REJ03B0023-0302