4552 Datasheet, PDF (69/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
Clock control register RG
RG2 Sub-clock (f(XCIN)) control bit (Note 2)
RG1 ^{Main-clock (f(XIN)) control bit (Note 2)}
On-chip oscillator (f(RING)) control bit
RG0
(Note 2)
at reset : 0002
at power down : state retained
W
TRGA
0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
0 Main clock (f(XIN)) oscillation available
1 Main clock (f(XIN)) oscillation stop
0 On-chip oscillator (f(RING)) oscillation available
1 On-chip oscillator (f(RING)) oscillation stop
Timer control register PA
PA0 Prescaler control bit
at reset : 02
0
Stop (state retained)
1
Operating
at power down : 02
W
TPAA
Timer control register W1
W13 ^{Timer 1 count auto-stop circuit selection}
bit (Note 3)
at reset : 00002
at power down : state retained
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
R/W
TAW1/TW1A
W12 _{Timer 1 control bit}
0 Stop (state retained)
1 Operating
W11 W10
Count source
W11
0 0 PWM signal (PWMOUT)
Timer 1 count source selection bits
W10 (Note 4)
0 1 Prescaler output (ORCLK)
1 0 Timer 3 underflow signal (T3UDF)
1 1 CNTR input
Timer control register W2
W23 CNTR pin output control bit
W22
PWM signal interrupt valid waveform/
return level selection bit
W21 _{Timer 2 control bit}
W20 _{Timer 2 count soruce selection bit}
at reset : 00002
at power down : 00002
0 CNTR pin output invalid
1 CNTR pin output valid
0 PWM signal “H” interval expansion function invalid
1 PWM signal “H” interval expansion function valid
0 Stop (state retained)
1 Operating
0
XIN input
1 Prescaler output (ORCLK)/2 signal output
R/W
TAW2/TW2A
Timer control register W3
at reset : 00002
at power down : state retained
W33 ^{Timer 3 count auto-stop circuit selection}
bit
0
XCIN input
1 Prescaler output (ORCLK)
W32 _{Timer 3 control bit}
0 Stop (Initial state)
1 Operating
W31
Timer 3 count value selection bits
W31 W30
Count value
0 0 Underflow occurs every 8192 counts
0 1 Underflow occurs every 16384 counts
W30
1 0 Underflow occurs every 32768 counts
1 1 Underflow occurs every 65536 counts
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: The oscillation circuit selected for system clock cannot be stopped.
3: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
4: Port C output is invalid when CNTR input is selected for the timer 1 count source.
R/W
TAW3/TW3A
Rev.3.02 Dec 22, 2006 page 69 of 142
REJ03B0023-0302