4552 Datasheet, PDF (25/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
EXTERNAL INTERRUPTS
The 4552 Group has the external 0 interrupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated conditions
Name
Input pin
Activated condition
External 0 interrupt D5/INT
When the next waveform is input to D5/INT pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
(Note 1)
D5/INT
I13
I12
Falling
0
1
Rising
K20
One-sided edge
I11
detection circuit
0
1
Both edges
detection circuit
(Note 2)
Level detection circuit
(Note 3)
Edge detection circuit
EXF0
External 0
interrupt
Timer 1 count start
synchronous circuit
K21
0
Key-on wakeup
1
Skip decision
(SNZI0 instruction)
Notes 1:
This symbol represents a parasitic diode on the port.
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
Rev.3.02 Dec 22, 2006 page 25 of 142
REJ03B0023-0302