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4552 Datasheet, PDF (66/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
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4552 Group
18 D5/INT pin
ⶠNote [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
⸠Note on bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
⢠Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 64â)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 64â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 64â).
⢠Depending on the input state of the D5/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to â0â (refer to Figure 66â)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 66â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 66â).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Control of INT pin input is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; Interrupt valid waveform is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 64 External 0 interrupt program example-1
â : these bits are not used here.
Fig. 66 External 0 interrupt program example-3
â· Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
⢠When the key-on wakeup function of INT pin is not used (register
K20 = â0â), clear bits 2 and 3 of register I1 before system enters
to the power down mode. (refer to Figure 65â).
LA 0
TI1A
DI
EPOF
POF2
; (00ââ2)
; Input of INT disabled ........................ â
; Power down mode
â : these bits are not used here.
Fig. 65 External 0 interrupt program example-2
Rev.3.02 Dec 22, 2006 page 66 of 142
REJ03B0023-0302
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