4552 Datasheet, PDF (54/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
E
Clock operating mode
POF instruction
execution
Key-on wakeup
(Stabilizing time c )
High-speed mode
CRCK instruction no execution
B
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
Ceramic resonator
POF instruction
execution
Key-on wakeup
(Stabilizing time d )
CRCK instruction execution
C
Operation state
• Operation source clock: f(XIN)
• Oscillation circuit:
RC oscillation
MR1, MR0←01
MR1, MR0←00
Internal mode
POF instruction
execution
(Stabilizing time a )
Key-on wakeup
(Stabilizing time b )
A
Operation state
• Operation source clock:
f(RING)
• Oscillation circuit:
On-chip oscillator
MR1, MR0←10
Low-speed mode
MR1, MR0←00
f(RING): stop
f(XIN): stop
f(XCIN): operating
POF instruction
execution
Key-on wakeup
(Stabilizing time e )
D
Operation state
• Operation source clock:
f(XCIN)
• Oscillation circuit:
Quartz-crystal oscillation
POF2 instruction
execution
F
Power down mode
Key-on wakeup
(Stabilizing time c )
POF2 instruction
execution
Key-on wakeup
(Stabilizing time d )
POF2 instruction
execution
Key-on wakeup
(Stabilizing time b )
POF2 instruction
execution
Key-on wakeup
(Stabilizing time e )
f(RING): stop
f(XIN): stop
f(XCIN): stop
Stabilizing time a : Microcomputer starts its operation after counting the f(RING) to 1376 times.
Stabilizing time b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio ✕ 15) times.
Stabilizing time c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 171) times.
Stabilizing time d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio ✕ 15) times.
Stabilizing time e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio ✕ 171) times.
Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down.
The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and
RG before transition to the power down state.
2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state.
3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state.
4: The state after system is released from reset;
• A ceramic oscillation is selected as the main clock (f(XIN)).
• Main clock (f(XIN)) and Suc-clock (f(XCIN)) are valid.
5: When the RC oscillation circuit is used, executing the CRCK instruction is required.
If the CRCK instruction is not executed, the ceramic oscillation is selected as the main clock f(XIN).
6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG,
and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
Fig. 44 State transition
POF or
EPOF instruction + _POF2
instruction
Reset input
Power down flag P
SQ
R
POF or
q Set source ^{• • • • • • •} EPOF instruction + POF2
instruction
q Clear source• • • • • • Reset input
Fig. 45 Set source and clear source of the P flag
Rev.3.02 Dec 22, 2006 page 54 of 142
REJ03B0023-0302
Program start
P = “1”
?
No
Cold start
Yes
Yes
Warm start
T3F = “1”
?
No
Return from
timer 3 underflow
Return from
external wakeup signal
Fig. 46 Start condition identified example using the SNZP instruction