4552 Datasheet, PDF (68/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
CONTROL REGISTERS
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
V10 External 0 interrupt enable bit
Interrupt control register V2
V23 ^{Not used}
V22 ^{Not used}
V21 ^{Not used}
V20 ^{Timer 3 interrupt enable bit}
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
at power down : 00002
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV1/TV1A
R/W
TAV2/TV2A
Interrupt control register I1
I13 INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 3)
I11 INT pin edge detection circuit control bit
INT pin Timer 1 count start synchronous
I10
circuit selection bit
at reset : 00002
at power down : state retained
R/W
TAI1/TI1A
0
INT pin input disabled
1
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Clock control register MR
at reset : 11002
at power down : state retained
MR3
MR2
Operation mode selection bits
MR3
MR2
System clock selection bits (Note 3)
MR3 MR2
Operation mode
0 0 Through mode
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
MR1 MR0
System clock
0 0 _f(RING)
0 1 _f(XIN)
1 0 _f(XCIN)
1 1 _{Not available (Note 4)}
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
3: The stopped clock cannot be selected for system clock.
4: “11” cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
R/W
TAMR/
TMRA
Rev.3.02 Dec 22, 2006 page 68 of 142
REJ03B0023-0302