4552 Datasheet, PDF (56/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
PU03
PU02
PU01
PU00
Pull-up control register PU0
Port P03 pull-up transistor
control bit
Port P02 pull-up transistor
control bit
Port P01 pull-up transistor
control bit
Port P00 pull-up transistor
control bit
PU13
PU12
PU11
PU10
Pull-up control register PU1
Port P13 pull-up transistor
control bit
Port P12 pull-up transistor
control bit
Port P11 pull-up transistor
control bit
Port P10 pull-up transistor
control bit
at reset : 00002
at power down : state retained
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
at reset : 00002
at power down : state retained
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
R/W
TAPU0/
TPU0A
R/W
TAPU1/
TPU1A
Interrupt control register I1
I13 INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
I11 INT pin edge detection circuit control bit
INT pin Timer 1 count start synchronous
I10
circuit selection bit
at reset : 00002
at power down : state retained
0
INT pin input disabled
R/W
TAI1/TI1A
1
INT pin input enabled
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
0
One-sided edge detected
1
Both edges detected
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
Rev.3.02 Dec 22, 2006 page 56 of 142
REJ03B0023-0302