4552 Datasheet, PDF (137/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
ELECTRICAL CHARACTERISTICS
(One Time PROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 3.6 V, unless otherwise noted)
Symbol
Parameter
Test conditions
VOH
“H” level output voltage
VDD = 3 V
IOH = –5 mA
P0, P1, P2, D0–D5
IOH = –1 mA
VOH
“H” level output voltage
VDD = 3 V
IOH = –10 mA
C, CNTR
IOH = –3 mA
VOL
“L” level output voltage
VDD = 3 V
IOL = 9 mA
P0, P1, P2, D0–D7, C, CNTR
IOL = 3 mA
VOL
“L” level output voltage
VDD = 3 V
IOL = 2 mA
RESET
IIH
“H” level input current
VI = VDD
P0, P1, P2, D0–D5, XIN, XCIN, RESET
CNTR, INT
IIL
“L” level input current
VI = 0 V P0, P1 No pull-up
P0, P1, P2, D0–D5, XIN, XCIN, RESET
CNTR, INT
RPU
Pull-up resistor value
VI = 0 V
P0, P1, RESET
VDD = 3 V
VT+ – VT– Hysteresis RESET
VDD = 3 V
VT+ – VT– Hysteresis INT
VDD = 3 V
VT+ – VT– Hysteresis CNTR
VDD = 3 V
f(RING) On-chip oscillator clock frequency
VDD = 3 V
∆f(XIN) Frequency error
VDD = 3 V ± 10 %, Ta = 25 °C
(with RC oscillation,
error of external R, C not included )
(Note 1)
RCOM COM output impedance (Note 2)
VDD = 3 V
RSEG SEG output impedance (Note 2)
VDD = 3 V
RVLC Internal resistor for LCD power supply
When dividing resistor 2r ✕ 3 selected
When dividing resistor 2r ✕ 2 selected
When dividing resistor r ✕ 3 selected
When dividing resistor r ✕ 2 selected
IDD
Supply current at active mode
VDD = 3 V
f(STCK) = f(XIN)/8
(with a ceramic resonator) f(XIN) = 4 MHz
f(STCK) = f(XIN)/4
f(RING) = stop
f(STCK) = f(XIN)/2
f(XCIN) = stop
f(STCK) = f(XIN)
at active mode
VDD = 3 V
f(STCK) = f(RING)/8
(with an on-chip oscillator) f(XIN) = stop
f(STCK) = f(RING)/4
f(RING) = active
f(STCK) = f(RING)/2
f(XCIN) = stop
f(STCK) = f(RING)
at active mode
VDD = 3 V
f(STCK) = f(XCIN)/8
(with a quartz-crystal
f(XIN) = stop
f(STCK) = f(XCIN)/4
oscillator)
f(RING) = stop
f(STCK) = f(XCIN)/2
f(XCIN) = 32 kHz
f(STCK) = f(XCIN)
at clock operation mode VDD = 3 V
(POF instruction execution) f(XCIN) = 32 kHz
at RAM back-up mode Ta = 25 °C
(POF2 instruction execution) VDD = 3 V
Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C).
2: The impedance state is the resistor value of the output voltage.
at VLC3 level output: VO = 0.8 VLC3
at VLC2 level output: VO = 0.8 VLC2
at VLC1 level output: VO = 0.2 VLC2 + VLC1
at VSS level output: VO = 0.2 VSS
Rev.3.02 Dec 22, 2006 page 137 of 142
REJ03B0023-0302
Limits
Unit
Min. Typ. Max.
2.1
V
2.4
2.1
V
2.4
1.4 V
0.9
0.9 V
2
µA
–2 µA
50 120 250 kΩ
0.4
V
0.3
V
0.2
V
100 250 400 kHz
±17 %
2
10 kΩ
2
10 kΩ
300 480 960 kΩ
200 320 640
150 240 480
100 160 320
0.3 0.6 mA
0.4 0.8
0.6 1.2
0.9 1.8
12 24 µA
17 34
27 54
48 96
5
10 µA
6
12
7
14
9
18
5
10 µA
0.1
2
µA
6