4552 Datasheet, PDF (23/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(6) Interrupt control registers
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
• Interrupt control register V2
The timer 3 interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruc-
tion. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.
Table 6 Interrupt control registers
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
V10 External 0 interrupt enable bit
at reset : 00002
at power down : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
0
This bit has no function, but read/write is enabled.
1
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
R/W
TAV1/TV1A
Interrupt control register V2
at reset : 00002
at power down : 00002
0
V23 ^{Not used}
1
0
V22 ^{Not used}
1
0
V21 ^{Not used}
1
0
V20 ^{Timer 3 interrupt enable bit}
1
Note: “R” represents read enabled, and “W” represents write enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
R/W
TAV2/TV2A
Rev.3.02 Dec 22, 2006 page 23 of 142
REJ03B0023-0302