4552 Datasheet, PDF (74/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
INSTRUCTIONS
The 4552 Group has the 124 (123) instructions. Each instruction is
described as follows;
(1) Index list of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of instruc-
tion function and the machine instructions.
Symbol
A
B
DR
E
V1
V2
I1
MR
RG
PA
W1
W2
W3
W4
L1
L2
L3
C1
C2
PU0
PU1
FR0
FR1
FR2
K0
K1
K2
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
UPTF
RPS
R1
R3
R2L
R2H
RLC
Contents
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Clock control register MR (4 bits)
Clock control register RG (3 bits)
Timer control register PA (1 bit)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
LCD control register L1 (4 bits)
LCD control register L2 (4 bits)
LCD control register L3 (4 bits)
LCD control register C1 (4 bits)
LCD control register C2 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Port output structure control register FR0 (4 bits)
Port output structure control register FR1 (4 bits)
Port output structure control register FR2 (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
High-order bit reference enable flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer LC reload register (4 bits)
Symbol
PS
T1
T2
T3
TLC
T1F
T2F
T3F
WDF1
WEF
INTE
EXF0
P
D
P0
P1
P2
C
x
y
z
p
n
i
j
A3A2A1A0
←
↔
?
()
—
M(DP)
a
p, a
C
+
x
Contents
Prescaler
Timer 1
Timer 2
Timer 3
Timer LC
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
Power down flag
Port D (8 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (4 bits)
Port C (1 bit)
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
Direction of data movement
Data exchange between a register and memory
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p6 p5 p4 p3 p2 p1 p0
Hex. C + Hex. number x
Note : Some instructions of the 4552 Group has the skip function to unexecute the next described instruction. The 4552 Group just invalidates the next instruc-
tion when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip
is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.3.02 Dec 22, 2006 page 74 of 142
REJ03B0023-0302