4552 Datasheet, PDF (39/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
q^{Waveform extension function of CNTR output “H” interval: Invalid (W22 = “0”),}
CNTR output: valid (W23 = “1”),
Count source: XIN input selected (W20 = “0”),
Reload register R2L: “0316”
Reload register R2H: “0216”
Timer 2 count start timing
Machine cycle _Mi
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W21
Timer 2 count value
(Reload register)
Timer 2
underflow signal
PWM signal
Mi+1
Mi+2
TW2A instruction execution cycle (W21) ← 1
0316
(R2L)
0216 0116 0016 0216 0116 0016 0316 0216 0116
(R2H)
(R2L)
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle
Mi
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Mi+1
TW2A instruction execution cycle (W21) ← 0
Register W21
Timer 2 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R2H)
(R2L)
0216
(R2H)
Timer 2
underflow signal
PWM signal
(Note 1)
Mi+2
Timer 2 count stop timing
Notes 1: In order to stop timer 2 at CNTR output valid (W23 = “1”), avoid a timing when timer 2 underflows.
If these timings overlap, a hazard may occur in a CNTR output waveform.
2: At CNTR output valid, timer 2 stops after “H” interval of PWM signal set by reload register R2H is output.
Fig. 28 Timer 2 count start/stop timing
Rev.3.02 Dec 22, 2006 page 39 of 142
REJ03B0023-0302