4552 Datasheet, PDF (34/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with two timer 2 reload reg-
isters (R2L, R2H). Data can be set simultaneously in timer 2 and
the reload register R2L with the T2AB instruction. Data can be set
in the reload register R2H with the T2HAB instruction. The contents
of reload register R2L set with the T2AB instruction can be set to
timer 2 again with the T2R2L instruction. Data can be read from
timer 2 with the TAB2 instruction.
Stop counting and then execute the T2AB or TAB2 instruction to
read or set timer 2 data.
When executing the T2HAB instruction to set data to reload regis-
ter R2H while timer 2 is operating, avoid a timing when timer 2
underflows.
Timer 2 starts counting after the following process;
➀ set data in timer 2
➁ set count source by bit 0 of register W2, and
➂ set the bit 1 of register W2 to “1.”
When a value set in reload register R2L is n, timer 2 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2L, and count continues (auto-reload function).
When bit 3 of register W2 is set to “1”, timer 2 reloads data from re-
load register R2L and R2H alternately each underflow.
Timer 2 generates the PWM signal (PWMOUT) of the “L” interval
set as reload register R2L, and the “H” interval set as reload regis-
ter R2H. The PWM signal (PWMOUT) is output from CNTR pin.
When bit 2 of register W2 is set to “1” at this time, the interval
(PWM signal “H” interval) set to reload register R2H for the counter
of timer 2 is extended for a half period of count source.
In this case, when a value set in reload register R2H is n, timer 2
divides the count source signal by n + 1.5 (n = 1 to 255).
When this function is used, set “1” or more to reload register R2H.
When bit 1 of register W4 is set to “1”, the PWM signal output to
CNTR pin is switched to valid/invalid each timer 1 underflow. How-
ever, when timer 1 is stopped (bit 2 of register W1 is cleared to “0”),
this function is canceled.
Even when bit 1 of a register W2 is cleared to “0” in the “H” interval
of PWM signal, timer 2 does not stop until it next timer 2 underflow.
When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a
timing when timer 2 underflows.
(5) Timer 3 (interrupt function)
Timer 3 is a 16-bit binary down counter.
Timer 3 starts counting after the following process;
➀ set count value by bits 0 and 1 of register W3,
➁ set count source by bit 3 of register W3, and
➂ set the bit 2 of register W3 to “1.”
Once count is started, when timer 3 underflows (the set count
value is counted), the timer 3 interrupt request flag (T3F) is set to
“1”, and count continues.
Bit 4 of timer 3 can be used as the timer LC count source for the
LCD clock generating.
When bit 2 of register W3 is cleared to “0”, timer 3 is initialized to
“FFFF16” and count is stopped.
Timer 3 can be used as the counter for clock because it can be op-
erated at clock operating mode (POF instruction execution). When
timer 3 underflow occurs at clock operating mode, system returns
from the power down state.
When operating timer 3 during clock operating mode, set 1 cycle or
more of count source to the following period; from setting bit 2 of
register W3 to “1” till executing the POF instruction.
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload
register (RLC). Data can be set simultaneously in timer LC and the
reload register (RLC) with the TLCA instruction. Data cannot be
read from timer LC. Stop counting and then execute the TLCA in-
struction to set timer LC data.
Timer LC starts counting after the following process;
➀ set data in timer LC,
➁ select the count source with the bit 2 of register W4, and
➂ set the bit 3 of register W4 to “1.”
When a value set in reload register RLC is n, timer LC divides the
count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new data
is loaded from reload register RLC, and count continues (auto-re-
load function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
Rev.3.02 Dec 22, 2006 page 34 of 142
REJ03B0023-0302