4552 Datasheet, PDF (49/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, set the time for the supply voltage to
rise from 0 V to the minimum voltage of recommended operating
conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and VSS at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
100 µs or less
VDD (Note 3)
(Note 1)
(Note 2)
RESET pin
(Note 1)
Pull-up transistor
Power-on reset
circuit output
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
(only for H version)
Watchdog reset signal
Internal reset signal
WEF
SRST instruction
Reset
state
Power-on Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 39 Structure of reset pin and its peripherals,, and power-on reset operation
Table 13 Port state at reset
Name
D0–D4
D5/INT
XCIN/D6, XCOUT/D7
P00/SEG21–P03/SEG24
P10/SEG25–P13/SEG28
P20/SEG17–P23/SEG20
SEG0/VLC3–SEG2/VLC1
SEG3–SEG12, SEG14–SEG16
COM0–COM3
C/CNTR
Function
D0–D4
D5
XCIN, XCOUT
P00–P03
P10–P13
P20–P23
SEG0–SEG2
SEG3–SEG12, SEG14–SEG16
COM0–COM3
C
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
Sub-clock input
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
VLC3 (VDD) level
VLC3 (VDD) level
VLC3 (VDD) level
“L” (VSS) level
Rev.3.02 Dec 22, 2006 page 49 of 142
REJ03B0023-0302