4552 Datasheet, PDF(59/145 Page) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

4552 Datasheet, PDF (59/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

◁

4552 Group

(5) External clock

When the external clock signal is used as the main clock (f(XIN)),

connect the XIN pin to the clock source and leave XOUT pin open.

(Figure 52). Do not execute the CRCK instruction in program.

Be careful that the maximum value of the oscillation frequency

when using the external clock differs from the value when using the

ceramic resonator (refer to the recommended operating condition).

Also, note that the power down mode (POF and POF2 instructions)

cannot be used when using the external clock.

M34552

* Do not execute the CRCK

instruction in program.

XIN

XOUT VDD

VSS

External oscillation circuit

Fig. 52 External clock input circuit

(6) Sub-clock generating circuit f(XCIN)

Sub-clock signal f(XCIN) is obtained by externally connecting a

quartz-crystal oscillator. Connect this external circuit and a quartz-

crystal oscillator to pins XCIN and XCOUT at the shortest distance. A

feedback resistor is built in between pins XCIN and XCOUT (Figure 53).

XCIN pin and XCOUT pin are also used as ports D6 and D7, respec-

tively. The sub-clock oscillation circuit is invalid and the function of

ports D6 and D7 are valid by setting bit 2 of register RG to â1â.

When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to

VSS and leave XCOUT/D7 open.

M34552

Note: Externally connect a damping

XCIN

XCOUT

resistor Rd depending on the

oscillation frequency.

(A feedback resistor is built-in.)

Use the quartz-crystal manu-

facturerâs recommended value

because constants such as ca-

pacitance depend on the

CIN

COUT

resonator.

(7) Clock control register MR

through register A with the TMRA instruction. In addition, the TAMR

instruction can be used to transfer the contents of register MR to

(8) Clock control register RG

contents of this register through register A with the TRGA instruction.

Fig. 53 External quartz-crystal circuit

ROM ORDERING METHOD

1.Mask ROM Order Confirmation Form*

2.Mark Specification Form*

3.Data to be written to ROM... one floppy disk.

* For the mask ROM confirmation and the mark specifications, re-

fer to the âRenesas Technology Corp.â Homepage

(http://www.renesas.com/homepage.jsp).

Table 18 Clock control registers

Clock control register MR

MR3

MR2

Operation mode selection bits

MR3

MR2

System clock selection bits (Note 2)

at reset : 11002

at power down : state retained

MR3 MR2

Operation mode

0 0 Through mode

0 1 Frequency divided by 2 mode

1 0 Frequency divided by 4 mode

1 1 Frequency divided by 8 mode

MR1 MR0

System clock

0 0 f(RING)

0 1 f(XIN)

1 0 f(XCIN)

1 1 Not available (Note 3)

R/W

TAMR/

TMRA

Clock control register RG

at reset : 0002

at power down : state retained

TRGA

RG2 Sub-clock (f(XCIN)) control bit (Note 4)

0 Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected

1 Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected

RG1 Main-clock (f(XIN)) control bit (Note 4)

0 Main clock (f(XIN)) oscillation available

1 Main clock (f(XIN)) oscillation stop

On-chip oscillator (f(RING)) control bit

RG0

(Note 4)

0 On-chip oscillator (f(RING)) oscillation available

1 On-chip oscillator (f(RING)) oscillation stop

Notes 1: âRâ represents read enabled, and âWâ represents write enabled.

2: The stopped clock cannot be selected for system clock.

3: â11â cannot be set to the low-order 2 bits (MR1, MR0) of register MR.

4: The oscillation circuit selected for system clock cannot be stopped.

Rev.3.02 Dec 22, 2006 page 59 of 142

REJ03B0023-0302

▷