4552 Datasheet, PDF (24/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10, V12, V13, V20), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are sat-
isfied on execution of other than one-cycle instructions (Refer to
Figure 16).
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
System clock
(STCK)
1 machine cycle
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
Interrupt enable
flag (INTE)
EI instruction execution cycle
Interrupt enabled state
Interrupt disabled state
External
interrupt
INT
EXF0
Timer 1,
Timer 2,
Timer 3
interrupts
T1F,T2F,T3F
Interrupt activated
condition is satisfied.
Retaining level of system
clock for 4 periods or more
is necessary.
Flag cleared
2 to 3 machine cycles
(Notes 1, 2)
The program starts
from the interrupt
address.
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
Rev.3.02 Dec 22, 2006 page 24 of 142
REJ03B0023-0302