4552 Datasheet, PDF (26/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure 16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an in-
terrupt occurs or when the next instruction is skipped with the skip
instruction.
(2) External interrupt control registers
• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter-
rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.
➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input
enabled state.
➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➄ Set both the external 0 interrupt enable bit (V10) and the INTE
flag to “1.”
The external 0 interrupt is now enabled. Now when a valid wave-
form is input to the D5/INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.
Table 8 External interrupt control register
Interrupt control register I1
I13 INT pin input control bit (Note 2)
at reset : 00002
at power down : state retained
0
INT pin input disabled
1
INT pin input enabled
R/W
TAI1/TI1A
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Falling waveform/“L” level (“L” level is recognized with the SNZI0
0
instruction)
Rising waveform/“H” level (“H” level is recognized with the SNZI0
1
instruction)
I11 INT pin edge detection circuit control bit
0
One-sided edge detected
1
Both edges detected
INT pin Timer 1 count start synchronous
I10
circuit selection bit
0
Timer 1 count start synchronous circuit not selected
1
Timer 1 count start synchronous circuit selected
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of these bits (I12 , I13) are changed, the external interrupt request flag (EXF0) may be set.
Rev.3.02 Dec 22, 2006 page 26 of 142
REJ03B0023-0302