4552 Datasheet, PDF (117/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
Skip condition
Datailed description
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V10 = 0: (EXF0) = 1
(INT) = “H”
However, I12 = 1
(INT) = “L”
However, I12 = 0
– Clears (0) to interrupt enable flag INTE, and disables the interrupt.
– Sets (1) to interrupt enable flag INTE, and enables the interrupt.
– When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1.” When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1)
– When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” (I12: bit 2 of interrupt control reg-
ister I1)
– When I12 = 0 : Skips the next instruction when the level of INT pin is “L.”
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– Transfers the contents of interrupt control register V1 to register A.
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– Transfers the contents of register A to interrupt control register V1.
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– Transfers the contents of interrupt control register V2 to register A.
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– Transfers the contents of register A to interrupt control register V2.
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– Transfers the contents of interrupt control register I1 to register A.
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– Transfers the contents of register A to interrupt control register I1.
Rev.3.02 Dec 22, 2006 page 117 of 142
REJ03B0023-0302