4552 Datasheet, PDF (8/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
PORT BLOCK DIAGRAMS
Register Y
Decoder
Skip decision
SZD instruction
SD instruction
RD instruction
CLD ^{(Note 3) FR1i}
instruction
S
RQ
Register Y
Decoder
Skip decision
SZD instruction
SD instruction
RD instruction
CLD
instruction
FR20
S
RQ
(Note 1)
D0—D3 (Note 2)
(Note 1)
(Note 1)
D4 (Note 2)
(Note 1)
Register Y
Decoder
Skip decision
SZD instruction
SD instruction
RD instruction
CLD
instruction
FR21
S
RQ
External 0 interrupt
Key-on wakeup input
Timer 1 count start synchronous circuit input
(Note 4)
External 0 interrupt circuit
(Note 1)
D5/INT (Note 2)
(Note 1)
Notes 1:
This symbol represents a parasitic diode on the port.
2: Applied potential to these ports must be VDD or less.
3: i represents bits 0 to 3.
4: As for details, refer to the external interrupt structure.
Port block diagram (1)
Rev.3.02 Dec 22, 2006 page 8 of 142
REJ03B0023-0302