4552 Datasheet, PDF (127/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Symbol
Parameter
Conditions
VDD
VDD
VDD
VRAM
VSS
VLC3
VIH
Supply voltage
(when ceramic resonator is used)
Supply voltage
(when quartz-crystal/on-chip
oscillation is used)
Supply voltage
(when RC oscillation is used)
RAM back-up voltage
Supply voltage
LCD power supply (Note 1)
“H” level input voltage
f(STCK) ≤ 6 MHz
f(STCK) ≤ 4.4 MHz
f(STCK) ≤ 2.2 MHz
f(STCK) ≤ 1.1 MHz
f(STCK) ≤ 4.4 MHz
at RAM back-up mode
P0, P1, P2, D0–D5
XIN, XCIN
VIL
“L” level input voltage
IOH(peak) “H” level peak output current
IOH(avg) “H” level average output current
(Note 2)
IOL(peak) “L” level peak output current
IOL(avg) “L” level average output current
(Note 2)
ΣIOH(avg) “H” level total average current
ΣIOL(avg) “L” level total average current
RESET
INT
CNTR
P0, P1, P2, D0–D5
XIN, XCIN
RESET
INT
CNTR
P0, P1, P2, D0–D5
VDD = 5 V
VDD = 3 V
C
VDD = 5 V
CNTR
VDD = 3 V
P0, P1, P2, D0–D5
VDD = 5 V
VDD = 3 V
C
VDD = 5 V
CNTR
VDD = 3 V
P0, P1, P2, D0–D7, C
VDD = 5 V
CNTR
VDD = 3 V
RESET
VDD = 5 V
VDD = 3 V
P0, P1, P2, D0–D7, C
VDD = 5 V
CNTR
VDD = 3 V
RESET
VDD = 5 V
VDD = 3 V
P0, P1, P2, D0–D5, C, CNTR
P0, P1, P2, D0–D5, C, CNTR
D6, D7, RESET
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
2: The average output current is the average value during 100 ms.
Limits
Min.
Typ.
Max. ^Unit
4
5.5
V
2.7
5.5
2
5.5
1.8
5.5
1.8
5.5
V
2.7
5.5
V
1.6
V
0
V
1.8
VDD
V
0.8VDD
VDD
V
0.7VDD
VDD
0.85VDD
VDD
0.85VDD
VDD
0.8VDD
VDD
0
0.2VDD V
0
0.3VDD
0
0.3VDD
0
0.15VDD
0
0.15VDD
–20 mA
–10
–30
–15
–10 mA
–5
–20
–10
24
mA
12
10
4
15
mA
7
5
2
–40 mA
60
mA
60
Rev.3.02 Dec 22, 2006 page 127 of 142
REJ03B0023-0302