4552 Datasheet, PDF (28/145 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4552 Group
TIMERS
The 4552 Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set-
ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload reg-
ister, and count continues (auto-reload function).
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid-
ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.
F F1 6
n : Counter initial value
Count starts
Reload
n
1st underflow
Reload
2nd underflow
0016
Timer interrupt ^{“1”}
request flag ^{“0”}
n+1 count
Fig. 21 Auto-reload function
The 4552 Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed dividing frequency timer
• Timer LC : 4-bit programmable timer
• Watchdog timer : 16-bit fixed dividing frequency timer
(Timers 1, 2, and 3 have the interrupt function, respectively)
Prescaler and timers 1, 2, 3 and LC can be controlled with the
timer control registers PA, W1 to W4. The watchdog timer is a free
counter which is not controlled with the control register.
Each function is described below.
n+1 count
Time
An interrupt occurs or
a skip instruction is executed.
Rev.3.02 Dec 22, 2006 page 28 of 142
REJ03B0023-0302