MC68HC908GP32 Datasheet, PDF (77/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset Bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $FF after POR while IRQ = V_DD
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.4 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.
4.4.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MOTOROLA
Resets and Interrupts
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Technical Data
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