MC68HC908GP32 Datasheet, PDF (142/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Configuration Register (CONFIG)
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE:
When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a
delay longer than the enable time for the LVI. There is no period where
the MCU is not protected from a low power condition. However, when
using the short stop recovery configuration option, the 32-CGMXCLK
delay is less than the LVI’s turn-on time and there exists a period in
startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 9. Computer
Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Technical Data
140
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Configuration Register (CONFIG)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA