MC68HC908GP32 Datasheet, PDF (112/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
Technical Data
110
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f_VRS.
Modulating the voltage on the CGM/XFC pin changes the frequency
within this range. By design, f_VRS is equal to the nominal center-of-range
frequency, f_NOM, (38.4 kHz) times a linear factor, L, and a power-of-two
factor, E, or (L × 2^E)f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f_RCLK, and is fed to the PLL through a
programmable modulo reference divider, which divides f_RCLK by a
factor, R. The divider’s output is the final reference clock, CGMRDV,
running at a frequency, f_RDV = f_RCLK/R. With an external crystal
(30 kHz–100 kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30 kHz and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f_VCLK, is
fed back through a programmable prescale divider and a programmable
modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N.
The dividers’ output is the VCO feedback clock, CGMVDV, running at a
frequency, f_VDV = f_VCLK/(N × 2^P). (See 7.4.6 Programming the PLL for
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in 7.4.4 Acquisition and Tracking Modes. The value of the
external capacitor and the reference frequency determines the speed of
the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f_RDV. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Clock Generator Module (CGMC)
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