MC68HC908GP32 Datasheet, PDF (200/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Monitor ROM (MON)
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the
monitor code to allow enabling the PLL to generate the internal clock,
provided the reset vector is blank, when the device is being clocked by
a low-frequency crystal. This addition, which is enabled when IRQ is
held low out of reset, is intended to support serial communication/
programming at 9600 baud in monitor mode by stepping up the external
frequency (assumed to be 32.768 kHz) by a fixed amount to generate
the desired internal frequency (2.4576 MHz). Since this feature is
enabled only when IRQ is held low out of reset, it cannot be used when
the reset vector is not blank because entry into monitor mode in this case
requires V_TST on IRQ.
15.4.1 Entering Monitor Mode
Table 15-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or
9.8304 MHz with PTC3 high
– IRQ = V_TST (PLL off)
2. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ
pullup; PLL off)
3. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 32.768 kHz (crystal)
– IRQ = V_SS (this setting initiates the PLL to boost the external
32.768 kHz to an internal bus frequency of 2.4576 MHz)
If V_TST is applied to IRQ and PTC3 is low upon monitor mode entry
(above condition set 1), the bus frequency is a divide-by-two of the input
clock. If PTC3 is high with V_TST applied to IRQ upon monitor mode entry,
the bus frequency will be a divide-by-four of the input clock. Holding the
Technical Data
198
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Monitor ROM (MON)
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