MC68HC908GP32 Datasheet, PDF (125/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
CGMC Registers
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
Address: $0036
Bit 7
6
5
4
3
2
1
Read:
PLLF
PLLIE
PLLON BCS
Write:
PRE1 PRE0 VPR1
Reset: 0
0
1
0
0
0
0
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
Bit 0
VPR0
0
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MOTOROLA
Clock Generator Module (CGMC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
123