MC68HC908GP32 Datasheet, PDF(202/410 Page) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HC908GP32 Datasheet, PDF (202/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

◁

Freescale Semiconductor, Inc.

Monitor ROM (MON)

PTC3 pin low when entering monitor mode causes a bypass of a divide-

by-two stage at the oscillator only if VTST is applied to IRQ. In this event,

the CGMOUT frequency is equal to the CGMXCLK frequency, and the

OSC1 input directly generates internal bus clocks. In this case, the

OSC1 signal must have a 50% duty cycle at maximum bus frequency.

If entering monitor mode without high voltage on IRQ (above condition

set 2 or 3, where applied voltage is either VDD or VSS), then all port C pin

requirements and conditions, including the PTC3 frequency divisor

selection, are not in effect. This is to reduce circuit requirements when

performing in-circuit programming.

NOTE:

If the reset vector is blank and monitor mode is entered, the chip will see

an additional reset cycle after the initial POR reset. Once the part has

been programmed, the traditional method of applying a voltage, VTST, to

IRQ must be used to enter monitor mode.

The COP module is disabled in monitor mode based on these

conditions:

â¢ If monitor mode was entered as a result of the reset vector being

blank (above condition set 2 or 3), the COP is always disabled

regardless of the state of IRQ or RST.

â¢ If monitor mode was entered with VTST on IRQ (condition set 1),

then the COP is disabled as long as VTST is applied to either IRQ

or RST.

The second condition states that as long as VTST is maintained on the

IRQ pin after entering monitor mode, or if VTST is applied to RST after

the initial reset to get into monitor mode (when VTST was applied to IRQ),

then the COP will be disabled. In the latter situation, after VTST is applied

to the RST pin, VTST can be removed from the IRQ pin in the interest of

freeing the IRQ for normal functionality in monitor mode.

Figure 15-2 shows a simplified diagram of the monitor mode entry when

the reset vector is blank and just 1 x VDD voltage is applied to the IRQ

pin. An external oscillator of 9.8304 MHz is required for a baud rate of

9600, as the internal bus frequency is automatically set to the external

frequency divided by four.

Technical Data

200

MC68HC908GP32â¢MC68HC08GP32 â Rev. 6

Monitor ROM (MON)

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

▷