MC68HC908GP32 Datasheet, PDF (289/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
System Integration Module (SIM)
SIM Counter
19.4.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V_DD voltage falls to the LVI_TRIPF voltage. The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 + 32 CGMXCLK cycles.
Thirty-two CGMXCLK cycles later, the CPU is released from reset to
allow the reset vector sequence to occur. The SIM actively pulls down
the RST pin for all internal reset sources.
19.4.2.6 Monitor Mode Entry Module Reset (MODRST)
The monitor mode entry module reset (MODRST) asserts its output to
the SIM when monitor mode is entered in the condition where the reset
vectors are blank ($FF). (See 15.4.1 Entering Monitor Mode.) When
MODRST gets asserted, an internal reset occurs. The SIM actively pulls
down the RST pin for all internal reset sources.
19.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
19.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MOTOROLA
System Integration Module (SIM)
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Technical Data
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