MC68HC908GP32 Datasheet, PDF (129/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
CGMC Registers
7.6.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the
programming information for the high byte of the modulo feedback
divider.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
MUL11 MUL10 MUL9 MUL8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback
divider that selects the VCO frequency multiplier N. (See 7.4.3 PLL
Circuits and 7.4.6 Programming the PLL.) A value of $0000 in the
multiplier select registers configures the modulo feedback divider the
same as a value of $0001. Reset initializes the registers to $0040 for
a default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
Bit7–Bit4 — Unimplemented Bits
These bits have no function and always read as logic 0s.
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MOTOROLA
Clock Generator Module (CGMC)
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Technical Data
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