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MC68HC908GP32 Datasheet, PDF (52/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)
Memory Map
Freescale Semiconductor, Inc.
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Configuration Register 2 Read: 0
0
0
0
0
0
OSC- SCIBD-
$001E
(CONFIG2)† Write:
STOPENB SRC
Reset: 0
0
0
0
0
0
0
0
$001F
Read:
Configuration Register 1
(CONFIG1)†
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3†
0
0
0
0
SSREC
0
STOP
0
COPD
0
Timer 1 Status and Control Read: TOF
TOIE TSTOP
0
0
$0020
Register Write: 0
TRST
(T1SC) Reset: 0
0
1
0
0
PS2
PS1
PS0
0
0
0
$0021
Timer 1 Counter Read: Bit 15
14
13
12
11
10
Register High Write:
(T1CNTH) Reset: 0
0
0
0
0
0
9
Bit 8
0
0
$0022
Timer 1 Counter Read: Bit 7
6
5
4
3
2
1
Bit 0
Register Low Write:
(T1CNTL) Reset: 0
0
0
0
0
0
0
0
Timer 1 Counter Modulo Read: Bit 15
14
13
12
11
10
$0023
Register High Write:
(T1MODH) Reset: 1
1
1
1
1
1
9
Bit 8
1
1
Timer 1 Counter Modulo Read: Bit 7
6
5
4
3
2
1
Bit 0
$0024
Register Low Write:
(T1MODL) Reset: 1
1
1
1
1
1
1
1
Timer 1 Channel 0 Status Read:
$0025 and Control Register Write:
(T1SC0) Reset:
CH0F
0
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B ELS0A
0
0
TOV0 CH0MAX
0
0
$0026
Timer 1 Channel 0 Read: Bit 15
14
Register High Write:
(T1CH0H) Reset:
13
12
11
10
Indeterminate after reset
9
Bit 8
Timer 1 Channel 0 Read: Bit 7
6
$0027
Register Low Write:
(T1CH0L) Reset:
5
4
3
2
Indeterminate after reset
1
Bit 0
† One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
= Unimplemented R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Technical Data
50
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Memory Map
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