MC68HC908GP32 Datasheet, PDF (404/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

MC68HC08GP32
Freescale Semiconductor, Inc.
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
OSC- SCIBD-
STOPENB SRC
Write:
Reset:
Mask defined
Figure A-3. Mask Option Register 2 (MOR2)
Address: $001F
Bit 7
6
5
4
3
2
1
Read: COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC STOP
Write:
Reset:
Mask defined
Figure A-4. Mask Option Register 1 (MOR1)
Bit 0
COPD
The bit functions for these two registers are the same as the
configuration registers in MC68HC908GP32 (see Section 8.
Configuration Register (CONFIG)).
A.6 Reserved Registers
The two registers at $FE08 and $FF7E are reserved locations on the
MC68HC08GP32.
On the MC68HC908GP32, these two locations are the FLASH control
register and the FLASH block protect register respectively.
A.7 Monitor ROM
The monitor program (monitor ROM, $FE20–$FF52) on the
MC68HC08GP32 is for device testing only.
The monitor mode entry by blank reset vector bit, MODRST bit (bit 2 at
$FE01), is not used in the ROM device — the reset vector will always
contain data in the MC68HC08GP32.
Technical Data
402
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MC68HC08GP32
For More Information On This Product,
Go to: www.freescale.com
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