MC68HC908GP32 Datasheet, PDF (124/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
• PLL VCO range select register (PMRS)
(See 7.6.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 7.6.6 PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr. Register Name
Bit 7
6
5
4
3
2
$0036
Read:
PLLF
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
PRE1
0
PRE0
0
PLL Bandwidth Control ^Read: _AUTO ^LOCK
ACQ
0
0
0
$0037
Register Write:
(PBWC) _{Reset: 0}
0
0
0
0
0
PLL Multiplier Select High ^{Read: 0}
0
0
0
MUL11 MUL10
$0038
Register Write:
(PMSH) _{Reset: 0}
0
0
0
0
0
PLL Multiplier Select Low ^Read:
$0039
Register Write:
(PMSL) _Reset:
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
MUL2
0
$003A
PLL VCO Range Select ^Read:
Register Write:
(PMRS) _Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
VRS3
0
VRS2
0
PLL Reference Divider ^{Read: 0}
0
0
0
RDS3 RDS2
$003B
Select Register Write:
(PMDS) _{Reset: 0}
0
0
0
0
0
= Unimplemented
R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
Technical Data
122
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Clock Generator Module (CGMC)
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