MC68HC908GP32 Datasheet, PDF (115/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
Functional Description
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t_ACQ (See 7.9 Acquisition/Lock Time
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
• Software must wait a given time, t_AL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGMC are disabled.
7.4.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f_BUSDES.
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f_VCLKDES = 4 × f_BUSDES
3. Choose a practical PLL (crystal) reference frequency, f_RCLK, and
the reference clock divider, R. Typically, the reference crystal is
32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f_RCLK/R. For
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency, f_VCLK, and the
reference frequency, f_RCLK, is
f_VCLK
=
2----^P_----N---
R
(
f_R
CL
K
)
MC68HC908GP32•MC68HC08GP32 — Rev. 6
MOTOROLA
Clock Generator Module (CGMC)
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Technical Data
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