MC68HC908GP32 Datasheet, PDF (192/410 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V_DD voltage. Clearing the LVI reset disable bit, LVIRSTD,
enables the LVI module to generate a reset when V_DD falls below a
voltage, V_TRIPF. Setting the LVI enable in stop mode bit, LVISTOP,
enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip
point bit, LVI5OR3, enables the trip point voltage, V_TRIPF, to be
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip
point voltage, V_TRIPF, to be configured for 3-V operation. The actual trip
points are shown in Section 23. Electrical Specifications.
NOTE:
After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5-V system is used, the user must set the LVI5OR3 bit to raise the
trip point to 5-V operation. Note that this must be done after every power-
on reset since the default will revert back to 3-V mode after each power-
on reset. If the V_DD supply is below the 5-V mode trip voltage but above
the 3-V mode trip voltage when POR is released, the part will operate
because V_TRIPF defaults to 3-V mode after a POR. So, in a 5-V system
care must be taken to ensure that V_DD is above the 5-V mode trip voltage
after POR is released.
NOTE:
If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on
reset while the V_DD supply is not above the V_TRIPR for 5-V mode, the
MCU will immediately go into reset. The LVI in this case will hold the part
in reset until either V_DD goes above the rising 5-V trip point, V_TRIPR,
which will release reset or V_DD decreases to approximately 0 V which will
re-trigger the power-on reset and reset the trip point to 3-V operation.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (CONFIG1). See 8.3 Functional Description for details of the
LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in
reset until V_DD rises above a voltage, V_TRIPR, which causes the MCU to
exit reset. See 19.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of
the interaction between the SIM and the LVI. The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
Technical Data
190
MC68HC908GP32•MC68HC08GP32 — Rev. 6
Low-Voltage Inhibit (LVI)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA