M38203M4 Datasheet, PDF (67/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing requirements 1
Table 17 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Limits
Unit
Min. Typ. Max.
2
µs
125
ns
45
ns
40
ns
250
ns
105
ns
105
ns
80
ns
80
ns
800
ns
370
ns
370
ns
220
ns
100
ns
1000
ns
400
ns
400
ns
200
ns
200
ns
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Timing requirements 2
Table 18 Timing requirements 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
Parameter
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
Limits
Unit
Min. Typ. Max.
2
µs
125
ns
45
ns
40
ns
500/
(VCC–2)
ns
twH(CNTR) CNTR0, CNTR1 input “H” pulse width
twL(CNTR) CNTR0, CNTR1 input “L” pulse width
250/
ns
(VCC–2)–20
250/
ns
(VCC–2)–20
twH(INT)
twL(INT)
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tc(SCLK2)
twH(SCLK2)
twL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
230
ns
230
ns
2000
ns
950
ns
950
ns
400
ns
200
ns
2000
ns
950
ns
950
ns
400
ns
300
ns
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).
3820GROUP USER’S MANUAL
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