M38203M4 Datasheet, PDF (141/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timer X and timer Y
(4) Timer Y latch and timer Y counter (TYL and TYH)
The timer Y latch (referred as “the Y latch”) and the timer Y counter (referred as “the Y counter”)
consist of 16 bits in a combination of high-order (address 002316) and low-order (address 002216).
The Y latch and Y counter are allocated at the same address. To access the Y latch and the Y
counter, access both the timer Y (low-order) and the timer Y (high-order).
sRead
When the timer Y (high-order and low-order) are read out, the value of the Y counter (count value)
are read out. Read both registers in the order of the timer Y (high-order) and the timer Y (low-order).
Do not write any value to the timer Y (high-order and low-order) before the timer Y (low-order) has
been read out. In this case, timer Y will not operate normally.
sWrite
When a value is written to the timer Y (low-order and high-order), the value is set in the Y latch and
the Y counter at the same time. Write the values to both registers in the order of the timer Y (low-
order) and the timer Y (high-order).
Do not read the timer Y (low-order and high-order) before the timer Y (high-order) has been written.
In this case, timer Y will not operate normally.
qTimer Y latch
The Y latch is a register which holds the value to be transferred (reloaded) automatically to the Y
latch as the initial value of the Y counter at the Y counter underflow. Figure 2.3.15 shows the
structure of the timer Y latch.
Reload is performed at the following :
•At the Y counter underflow
•At the edge of the input pulse from the P55/CNTR1 pin
(period measurement mode/pulse width HL coutinuously measurement mode)
The contents of the Y latch cannot be read out.
qTimer Y latch
Timer Y (high-order, low-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y (high-order, low-order) (TYH, TYL) [Address 2316, 2216]
B
Functions
At reset R W
0 ^{•Set “000016 to FFFF16” as timer Y count value.} 1 ^×
to ^{•Write high-order byte of setting value to TYH,}
7 ^{and low-order byte to TYL, respectively.}
•The values of TYH and TYL are set to the
respective Y latches and transferred auto-
matically to the respective Y counters at the
Y counter underflow.
Note : Write both registers in the order of TYL and TYH.
Fig. 2.3.15 Structure of timer Y latch
3820 GROUP USER’S MANUAL
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