M38203M4 Datasheet, PDF (272/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.10 Reset
The reset state is provided by applying a “L” level
to the RESET pin at power source voltage of 2.5 V
to 5.5 V. Allow 2 µs or more as “L” level applying
time.
By applying a “H” level to the RESET pin in the
internal reset state, the timers and their count source
shown in Table 2.10.1 is automatically set. After
that, the internal reset state is released by the timer
2 underflow.
After applying “H” level, only the main clock oscil-
lates in the middle-speed mode regardless of the
oscillation state previous to internal resetting. The
XCIN pin on the sub-clock side becomes the input
port.
After the internal reset state is released, the pro-
gram is run from the address determined with the
contents (high-order address) at address FFFD16
and the contents (low-order address) at address
FFFC16.
Figure 2.10.2 shows the internal processing sequence
immediately after reset release.
Table 2.10.1 Timers 1 and 2 at reset
Item
Timer 1
Timer 2
Value
FF16
0116
Count
source
f (XIN)/16
Timer 1 underflow
VCC
f(XIN)
1 µs at f(XIN) = 8 MHz
Internal clock
φ _{2 µs or more}
RESET
Approximately 8000 cycles of XIN input
Internal reset
Address bus
Data bus
FFFC16 FFFD16 AL,AH
AL AH
SYNC
Internal clock φ : CPU reference clock frequency = f(XIN)/8 (middle-speed mode
immediately after reset)
AH, AL : Interrupt jump destination addresses
SYNC ^{: CPU operation code fetch cycle}
(This is a internal signal, so that it cannot be observed from
the external unit)
: Undefined
Fig. 2.10.2 Internal processing sequence immediately after reset release
2–186
3820 GROUP USER’S MANUAL