M38203M4 Datasheet, PDF (106/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the
interrupt control register 2 (address 003F16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0,” the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0,” the corresponding interrupt request bit is only set to “1” and this
interrupt is not accepted.
In this case, unless the interrupt request bit is set to “0” by software, the interrupt request bit remains
in the “1” state.
When an interrupt enable bit is “1,” the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1,” this interrupt is accepted (at interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request.
When this flag is “1,” the acceptance of interrupt requests is disabled. When the flag is “0,” the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1,”
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.6 shows an example of multiple inter-
rupts.
Table 2.2.2 List of interrupt bits for individual interrupt sources
Interrupt sources
Interrupt request bit
Address
Bit
INT0
INT1
Serial I/O1 receive
Serial I/O1 transmit
Timer X
Timer Y
Timer 2
Timer 3
CNTR0
CNTR1
Timer 1
INT2
INT3
Key input
Serial I/O2
003C16
b0
003C16
b1
003C16
b2
003C16
b3
003C16
b4
003C16
b5
003C16
b6
003C16
b7
003D16
b0
003D16
b1
003D16
b2
003D16
b3
003D16
b4
003D16
b5
003D16
b6
Interrupt enable bit
Address
Bit
003E16
b0
003E16
b1
003E16
b2
003E16
b3
003E16
b4
003E16
b5
003E16
b6
003E16
b7
003F16
b0
003F16
b1
003F16
b2
003F16
b3
003F16
b4
003F16
b5
003F16
b6
2–20
3820 GROUP USER’S MANUAL