M38203M4 Datasheet, PDF (309/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
3.3 Control registers
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
LCD mode register (LM) [Address 3916]
B
Name
0 _{Duty ratio selection}
bits
1
2 ^{Bias control bit}
3 ^{LCD enable bit}
4 Fix this bit to “0.”
Functions
b1b0
00: Not available
01: 2 (use COM0, COM1)
10: 3 (use COM0–COM2)
11: 4 (use COM0–COM3)
0: 1/3 bias
1: 1/2 bias
0: LCD OFF
1: LCD ON
At reset R W
0
0
0
0
0 00
5 LCD circuit divider division ^b6b5
0
ratio selection bits (Note 1) ^{00: LCDCK count source}
01: 2 division of LCDCK count source
6
10: 4 division of LCDCK count source
11: 8 division of LCDCK count source
7 ^{LCDCK count source} 0: f(XCIN)/32
0
selection bit (Note 2) 1: f(XIN)/8192
Notes 1: Reference values at f(XIN) = 8 MHz
00: 977 Hz
01: 488 Hz
10: 244 Hz
11: 122 Hz
2: LCDCK is a clock for a LCD timing controller.
Fig. 3.3.15 Structure of LCD mode register
3820 GROUP USER’S MANUAL
3–25