M38203M4 Datasheet, PDF (145/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Timer X and timer Y
sCNTR0 active edge switch bit (bit 6)
The CNTR0 active edge switch bit has a function which selects an active edge of the CNTR0 interrupt,
and functions for each mode.
qCNTR0 interrupt
When bit 6 is “0,” the falling edge ( ) is active.
When bit 6 is “1,” the rising edge ( ) is active.
qPulse output mode
In the pulse output mode, the initial level at the start of pulse output is selected.
When bit 6 is “0,” the initial level is “H.”
When bit 6 is “1,” the initial level is “L.”
qEvent counter mode
An active edge of the count source is selected.
When bit 6 is “0,” the rising edge ( ) is active.
When bit 6 is “1,” the falling edge ( ) is active.
qPulse width measurement mode
A duration of pulse width measured is selected.
When bit 6 is “0,” the “H” level width is measured.
When bit 6 is “1,” the “L” level width is measured.
sTimer X stop control bit (bit 7)
The timer X stop control bit controls the count operation of the timer X.
By writing “0” to bit 7, a count source is input to the X counter, so that a count operation is started.
As bit 7 is in the “0” state immediately after reset release, the count operation is automatically started
after reset release.
By writing “1” to bit 7, the input of count source to the X counter is stopped, so that the count operation
stops.
In the pulse width measurement mode, however, a count operation is performed only in the period in
which the measurement level is input to the P54/CNTR0 pin when bit 7 is in the “0” state.
At read, this bit functions as a status bit to indicate the operating state (counting or stop) of the X
counter. When bit 7 is “0,” the counter is in the operating state. When bit 7 is “1,” the counter is in
the stop state.
3820 GROUP USER’S MANUAL
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