M38203M4 Datasheet, PDF (114/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.2 Interrupts
2.2.4 INT interrupts
The INT interrupt requests occur by detecting a level change of each INT pin (INT0–INT3).
(1) Active edge selection
As an active edge, falling edge ( ) detection or rising edge ( ) detection can be selected by bits
0 to 3 of the interrupt edge selection register (address 003A16).
In the “0” state, the falling edge of the corresponding pin is detected. In the “1” state, the rising edge
of the corresponding pin is detected.
The pins INT0 to INT3 are also used as I/O ports P42, P43, P57, and P60, but no register to switch
between INT pin and I/O port is available. When the port is an input port, the active edges of the port
are always detected. Accordingly, when using ports P42, P43, P57 and P60 as input ports, put the
corresponding INT interrupt into the disabled state. If this interrupt is not disabled, an INT interrupt is
caused by pin level change, so that the program runs away.
Figure 2.2.14 shows the structure of the interrupt edge selection register.
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address 3A16]
B
Name
Functions
0 INT0 interrupt edge
selection bit
1 INT1 interrupt edge
selection bit
2 INT2 interrupt edge
selection bit
3 INT3 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
4 Nothing is allocated. These bits cannot be
to written to and are fixed to “0” at reading.
7
At reset R W
0
0
0
0
0 0^×
Fig. 2.2.14 Structure of interrupt edge selection register
2–28
3820 GROUP USER’S MANUAL