M38203M4 Datasheet, PDF (278/344 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.11 Oscillation circuit
2.11.2 Internal clock φ
The internal clock φ is the standard for operations.
(1) Clock generating circuit
The clock generating circuit controls the oscillation of the oscillation circuit. The generated clock
(internal clock φ) is supplied to the CPU and peripheral units.
Figure 2.11.3 shows the clock generating circuit block diagram. Oscillation can be stopped and re-
sumed by the clock generating circuit.
XCIN
XCOUT
“1”
“0” ^{Port Xc}
switch bit
Timer 1
Timer 2
XIN
XOUT Internal system clock
count source
count source
selection bit (Note)
selection bit
selection bit
“1” ^{Low-speed mode}
1/2 1/4
1/2
“1” _{Timer 1 “0”}
Timer 2
“0”
“0”
“1”
Middle-/high-speed
mode
Main clock
division ratio
selection bit
Main clock
stop bit
“1” Middle-speed mode
“0”
High-/low-speed
mode
Timing φ
(Internal clock)
QS
R
STP
instruction
SQ
WIT _R
instruction
QS
R STP
instruction
Reset
Interrupt disable flag (I)
Interrupt request
Note: When using the low-speed mode, set the port Xc switch bit to “1.”
Fig. 2.11.3 Clock generating circuit block diagram
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3820 GROUP USER’S MANUAL